1. Field of the Invention
The present invention generally relates to a cache memory system including a small-capacity cache memory enabling high-speed access, which is provided between a processor and a main memory and more particularly, to a cache memory system for use in a multiprocessor in which a plurality of processors operate nonsynchronously.
2. Description of the Prior Art
FIG. 14 schematically shows an example of a configuration of a conventional cache memory system 100. In FIG. 14, the cache memory system 100 includes a cache memory unit 102 through which a processor 101 is connected to a main memory 103. The cache memory unit 102 is, in turn, constituted by a tag memory 105, a cache memory 106 and a cache controller 107 for controlling transfer of data to the cache memory 106 with reference to a correspondence table of tags stored in the tag memory 105.
On the other hand, in the cache memory system 100, access time varies according to whether or not data is stored, i.e., hit in the cache memory 106. Thus, in order to raise a cache hit ratio, a prefetch mechanism for preliminarily preparing data in the cache memory 106 may be provided in the cache controller 107. In such a cache memory system 100, in case data to be accessed exists in the cache memory 106, the data is supplied from the cache memory 106 to the processor 101. On the contrary, in case the data to be accessed does not exist in the cache memory 106, the data is supplied from the main memory 103 to the processor 101.
However, in the above mentioned configuration of the conventional cache memory system 100, even if the prefetch mechanism is used by static scheduling technique, it is impossible to achieve a cache hit ratio of 100%. Thus, it is difficult to perform nonsynchronous operation of multiple processors of a multiprocessor by using the conventional cache memory system 100 of FIG. 14 in the multiprocessor.